1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a dynamic random access memory (DRAM) in which a plurality of memory elements (memory cells) using capacitors and a fabrication method therefor, and, more particularly, to a semiconductor integrated circuit such as a DRAM having redundancy circuits that are incorporated in the semiconductor integrated circuit in order to prevent decreasing of the yield of semiconductor integrated circuits caused by wafer defects by electrically connecting or disconnecting the redundancy circuits based on connecting or cutting of fuse elements.
2. Description of the Prior Art
FIG. 8 is a diagram showing a sectional view of a conventional dynamic random access memory (DRAM) fabricated by using the technique disclosed in the Japanese laid open publication number JP-A-60/98665. In FIG. 8, the reference number 1 designates a semiconductor substrate on which semiconductor elements such as capacitors, resistors, and the like are formed, 2 denotes one electrode of a capacitor, 3 indicates an insulating layer in the capacitor, and 4 designates other electrode of the capacitor. The reference number 5 designates word lines and 6 indicates bit lines. The reference number 7 designates a first wiring of aluminum, 8 indicates a second wiring of aluminum. The reference number 9 designates a fuse element connected to the first wiring 7. The reference numbers 10 to 15 designate insulating layers for electrical insulating those circuit elements from each other such as the capacitors, for example.
The fuse element 9 is formed in a fabrication process for the bit lines 6 simultaneously. FIG. 8 shows only one fuse element for brevity. The left half in FIG. 8 designates a memory cell in which the capacitor including the electrodes 2 and 4 and the insulating layer 4 is located. The right half in FIG. 8 indicates a wiring section in which the fuse element 9 is included.
Next, a description will be given of the operation of the conventional semiconductor integrated circuit shown in FIG. 8.
When information is stored in the DRAM shown in FIG. 8, at first, a voltage corresponding to the information to be stored is supplied to the word line 5 through the first line and the second line 8. Then, a channel is formed between the semiconductor substrate 1 corresponding to the word line 5 and the electrode 2 of the capacitor, and a current flows to the electrode 2 of the capacitor from the word line 5 through the semiconductor substrate 1. After this, when the voltage supply to the word line 5 is stopped, electrical charge corresponding to the applied voltage is stored between the electrode 2 of the capacitor and the electrode 4 of the capacitor.
In addition, when information is read from the DRAM shown in FIG. 8, a voltage is supplied to the word line 5 through the first and second lines 7 and 8. Thereby, a channel is formed in a section between the word line 5 and the electrode 2 in the semiconductor substrate 1. Thereby, a current flows to the word line 5 from the electrode 2 in the capacitor through the semiconductor substrate 1. The value of the stored information is detected based on the magnitude of this current flow.
Next, a description will be given of the function of the fuse 9.
In general, defects in the wafer are generated in at a constant probability during a semiconductor fabrication process. This prevents increasing of the yield percentage. That is, there is a drawback that it is difficult to increase the yield percentage of the semiconductor fabrication process. In other words, there is the drawback that the yield rate of the semiconductor fabrication process is limited. In order to avoid this drawback, redundancy circuits are incorporated in each semiconductor integrated circuit such as DRAM and the like. For example, the redundancy circuits a DRAM are memory cells. When a defect of a memory cell is caused in a semiconductor integrated circuit fabricated during the semiconductor fabrication process, the memory cell as a defect circuit is replaced with a redundancy circuit by electrically connecting this redundancy circuit. This method prevents the decreasing of yield rate of the semiconductor integrated circuit. A plurality of fuse elements are incorporated in each semiconductor integrated circuit in order to increase the yield rate. The fuse is cut by using irradiation of a laser beam in order to replace a defective circuit with the redundant circuit (such as an added memory cell). This method may be used to increase the yield rate of semiconductor integrated circuits.
Because the conventional semiconductor integrated circuit has the above configuration, the level of the surface of the insulating layer 14 on the capacitor, made up of the electrodes 2 and 4 and the layer 3 in the memory section (see the left half in FIG. 8), is different from the level of the surface of the insulating layer 14 in the wiring section (see the right half in FIG. 8). In this case, as shown in FIG. 9, although a laser beam to be used for etching process for each layer is focused in one section (for example, the memory cell section), the laser beam is not focused (namely it causes off-focus) in other section (for example, the wiring section). Accordingly, it is difficult to form correctly the width of each wiring in the wiring section in off-focus section. Taking a concrete example, because the off-focus is caused in the wiring section in the semiconductor integrated circuit shown in FIG. 8, as shown in the right half in FIG. 9, the width of a wiring is increased from W1 to SW2 (W2&lt;W1). This increased width prevents increasing of the semiconductor integration.
In order to avoid the above conventional drawback, as shown in FIG. 10, there is a conventional method in which the thickness of the insulating layer 14 on the capacitor made up of the electrodes 2 and 4 and the layer 3 is increased in order that the surfaces of both the memory cell section (see the left half in FIG. 10) and the wiring section (see the right half in FIG. 10) having the same level. However, this conventional fabrication method causes a drawback in which the depth d2 of the fuse 9, measured from the surface of a semiconductor chip, becomes larger (see d2&gt;d1 in FIGS. 10, 11A, and 11B) than the depth d1 of the fuse 9 in the conventional semiconductor integrated circuit shown in FIG. 8. As a result, it is required to blow a laser beam deep in the semiconductor integrated circuit having the configuration shown in FIG. 11B. This causes an increase the length by the blowing time of the laser beam and increases the diameter of a hole formed by blowing of the laser beam. In order to avoid the drawback, it is required to increase a fabrication interval (W4) of the fuses 9. However, this prevents the integration of the semiconductor integrated circuit. That is, this becomes one of factors preventing increasing of the integration of the semiconductor integrated circuit.